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Texas Instruments LM3S5C36-IQR80-A2 — Microcontrollers & Processors (MCU / MPU / DSP)

Texas Instruments LM3S5C36-IQR80-A2 MCU, 80MHz, 512KB Flash

MPNLM3S5C36-IQR80-A2
Obsolete

Texas Instruments Stellaris® ARM® Cortex®-M3S 5000 series microcontroller, LM3S5C36-IQR80-A2, 80MHz, 512KB flash, 64KB RAM, 64-LQFP, -40°C to 85°C.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

LM3S5C36-IQR80-A2 specifications
ParameterValue
SeriesStellaris® ARM® Cortex®-M3S 5000
MountingSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))3V ~ 3.6V
Operating temperature-40°C~85°C(TA)
Speed80MHz
PackageTray
RAM size64K x 8
Core size32-Bit Single-Core
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDT
ConnectivityCANbus, I²C, IrDA, LINbus, Microwire, QEI, SPI, SSI, UART/USART, USB
Number of i (O)33
Core processorARM® Cortex®-M3
Case64-LQFP
Data convertersA/D 8x12b
Program memory size512KB (512K x 8)

Product details

64-LQFP footprint and board-fit

The LM3S5C36-IQR80-A2 ships in a 64-LQFP package with a 10x10 mm body. The 0.5 mm pitch on the 64-LQFP demands a 4-layer board for clean fan-out of the inner rows — a 2-layer board will struggle to route the supply and ground to the core without adding vias that eat into the keep-out zone.

Memory headroom and peripheral mix

The 80 MHz Cortex-M3 core delivers roughly 100 DMIPS, enough for real-time control loops and protocol parsing without a cache. The connectivity set includes USB, CAN, I²C, SPI, SSI, UART, and IrDA — a single part can bridge a CAN bus to a USB host and log data over UART simultaneously. 33 general-purpose I/O and an 8-channel 12-bit ADC cover sensor interfaces and simple human-machine interaction. The PWM and QEI peripherals suit motor-control feedback loops without an external FPGA.

Texas Instruments has marked the LM3S5C36-IQR80-A2 as obsolete. No official successor or pin-compatible replacement is recorded in the manufacturer's lifecycle data. RoHS compliance is standard for this date code; full compliance documentation is available per request.

Frequently asked questions

What is the speed of the LM3S5C36-IQR80-A2?

The core runs at 80 MHz. The Cortex-M3 pipeline sustains one instruction per clock on most operations, so the effective throughput is roughly 80 MIPS from flash with zero wait states at that speed.