TI LM3S5951-IQC80-C5 MCU, 80MHz, 256KB Flash, Stellaris Cortex-M3
MPNLM3S5951-IQC80-C5
Obsolete
Texas Instruments Stellaris LM3S5951-IQC80-C5, 32-bit ARM Cortex-M3 at 80MHz, 256KB Flash, 64KB RAM, USB OTG / CANbus / I²C / SPI, 100-LQFP package, -40°C to 85°C.
$7.2500Ref. price · indicative, final on quote
StockContact for availability
MOQ1 pcs
- 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
- Date & lot codes on quoteStated per line before you commit; label photos on request.
- MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
- PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.
Specifications
| Parameter | Value |
|---|---|
| Series | Stellaris® ARM® Cortex®-M3S 5000 |
| Mounting type | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 1.08V ~ 1.32V |
| Operating temperature | -40°C~85°C(TA) |
| Speed | 80MHz |
| Package | Tray |
| RAM size | 64K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT |
| Connectivity | CANbus, I²C, IrDA, LINbus, Microwire, QEI, SPI, SSI, UART/USART, USB OTG |
| Number of i (O) | 67 |
| Core processor | ARM® Cortex®-M3 |
| Case | 100-LQFP |
| Data converters | A/D 16x10b |
| Program memory size | 256KB (256K x 8) |
Frequently asked questions
Where can I buy the LM3S5951-IQC80-C5 and how is it quoted for volume purchases?
Independent distribution holds the available channel. Quotes are issued to order on request; lead time and any spot-premium context are confirmed against current stock at quote time.
What is the closest pin-compatible replacement for the LM3S5951-IQC80-C5?
No official L* successor or second-source order code appears in the record for this part. The STM32F107VCT6 (100-pin LQFP, Cortex-M3 at 72MHz, 256KB Flash) is the closest architectural peer in the broader ecosystem — verify pinout and peripheral mapping against the respective datasheets before committing a BOM change.