The 100-LQFP package provides 61 GPIOs, and an 8-channel 10-bit ADC is built in. This part targets industrial control nodes, motor drives, and automotive body electronics where CAN connectivity and a moderate memory footprint are required.
This is the official notice that while the part remains available for existing production builds, it is not intended for new design starts. For a buyer managing a BOM line that already uses this MCU, the NRND flag means you have time to secure last-time-buy quantities or qualify a replacement, but you should not commit a new project to this order code.
50 MHz Cortex-M3 — what the speed rating buys you
The 50 MHz core clock is the usual Cortex-M3 sweet spot for control-loop tasks that need more throughput than a 48 MHz Cortex-M0 but don't require the 80–120 MHz tier. With zero-wait-state Flash access at this frequency, the part can handle a CANopen stack, a USB device interface, and a PID loop without stalling the bus. The 64 KB SRAM gives enough headroom for double-buffered ADC data or a modest RTOS heap.