Cortex-M3 core with USB and serial connectivity
The LM3S3739-IQC50-A0: The 100-LQFP package (14×14 mm body) exposes 61 GPIO lines and an 8-channel 10-bit ADC.
NRND — last-time-buy planning window
Texas Instruments lists the LM3S3739-IQC50-A0 as NRND (Not Recommended for New Designs). This means the part is still available for existing production but is not intended for new design starts. For sustainment programs — medical, industrial, or defense — that already have this MCU in the BOM, the NRND status signals a last-time-buy window is likely.
On-chip peripherals and memory headroom
The 128 KB flash and 64 KB SRAM leave room for a real-time control loop with a USB stack and a modest RTOS footprint. The DMA controller offloads peripheral-to-memory transfers without stalling the Cortex-M3 core. Built-in brown-out detect, POR, and watchdog timer reduce external supervisor IC count. The internal oscillator keeps the BOM simple for applications that do not require a precision external clock source.
Package and board-fit notes
The 100-LQFP with 0.50 mm pitch and a 14×14 mm body requires a four-layer board for clean fan-out of the inner rows. Decoupling should follow the standard 100 nF per VDD pair plus a 10 µF bulk cap near the supply entry. The 2.25 V to 2.75 V supply rail is tight — a 2.5 V ±2% regulator is the natural match.