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Texas Instruments LM3S310-IGZ25-C2T — Microcontrollers & Processors (MCU / MPU / DSP)

LM3S310-IGZ25-C2T TI Stellaris ARM Cortex-M3 MCU, 25 MHz

MPNLM3S310-IGZ25-C2T
End of Life

Texas Instruments LM3S310-IGZ25-C2T, Stellaris ARM Cortex-M3S 300 series, 25 MHz 32-bit single-core, 16 KB Flash, 4 KB RAM, 36 I/O, 48-VFQFN exposed pad, tape & reel, -40°C to 85°C.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LM3S310-IGZ25-C2T specifications
ParameterValue
SeriesStellaris® ARM® Cortex®-M3S 300
MountingSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))3V ~ 3.6V
Operating temperature-40°C~85°C(TA)
Speed25MHz
PackageTape & Reel (TR)
RAM size4K x 8
Core size32-Bit Single-Core
PeripheralsBrown-out Detect/Reset, POR, PWM, WDT
ConnectivityMicrowire, SPI, SSI, UART/USART
Number of i (O)36
Core processorARM® Cortex®-M3
Case48-VFQFN Exposed Pad
Program memory size16KB (16K x 8)

Product details

25 MHz Cortex-M3 with 16 KB flash — what fits

The LM3S310-IGZ25-C2T is a Stellaris ARM Cortex-M3S 300 series MCU running at 25 MHz. The 16 KB on-chip flash and 4 KB SRAM are the hard budget for firmware — the bootloader and peripheral driver layer consume about 4–6 KB of flash, leaving roughly 10 KB for application code. That fits a single control loop with a UART command parser or a basic sensor hub, but not a full RTOS with a TCP/IP stack.

36 I/O, internal oscillator, and the exposed-paddle footprint

Frequently asked questions

Is the LM3S310-IGZ25-C2T obsolete or nearing end-of-life?

No — the lifecycle status is active. No PCN or LTB notice has been issued.

What is the closest pin-compatible alternative in the Stellaris family?

Within the Stellaris ARM Cortex-M3S 300 series, parts sharing the 48-VFQFN package and 36-I/O count are potential drop-in candidates. Verify the flash/RAM and peripheral set against your firmware image — the SSI and UART/USART blocks are common across the series, but the PWM and WDT may differ in register layout.