Texas Instruments lists the LM3S2739-IQC50-A2 as NRND (Not Recommended for New Designs). This means the part is still available for existing production but TI will not support it in new socket designs — a last-time-buy window is the typical next step, so existing BOM lines should plan a migration.
Core and memory — flash budget and RAM headroom
The ARM Cortex-M3 core runs at 50 MHz — enough throughput for a CAN-connected motor controller or a multi-protocol gateway aggregating I²C and SPI sensor buses. The 128 KB on-chip flash and 64 KB SRAM leave room for a real-time OS kernel plus the application stack; the 128 KB flash sector layout typically budgets 8–16 KB for a bootloader, leaving the rest for firmware. Program memory is FLASH type, field-upgradable via the bootloader if the firmware update strategy fits within the flash endurance (100 K erase/write cycles typical for the Stellaris family).
The LM3S2739 integrates a CANbus controller, two I²C interfaces, two SPI/SSI ports, a UART/USART, plus IrDA and Microwire support — covering the common fieldbus and serial sensor links in a single chip. The Quadrature Encoder Interface (QEI) is useful for closed-loop motor position feedback without an external encoder counter. On-chip peripherals include brown-out detect, POR, PWM, and watchdog timer. The 4-channel 10-bit ADC samples at the internal oscillator rate; for higher precision or simultaneous sampling, an external ADC on the SPI bus is straightforward. 56 GPIO lines in the 100-LQFP package give enough headroom for a parallel LCD interface or a bank of opto-isolated inputs alongside the serial interfaces.
The core and I/O share a single supply rail: 2.25 V to 2.75 V. This narrow window means the 2.5 V rail must be regulated — a standard 2.5 V LDO with 200 mV dropout works from a 3.3 V bus, but the headroom is tight. The internal oscillator eliminates the external crystal for the core clock, though the USB or CAN timing may still need an external resonator for accuracy.