The LM3S1Z16-IQR50-C5: It runs at 50 MHz from a single-core Cortex-M3, with 16 KB of program Flash and 6 KB of SRAM — enough for a single-loop motor controller, a sensor hub, or a protocol bridge in industrial or building-automation gear.
The 50 MHz core clock is the practical ceiling for this part — the Flash prefetch buffer and single-cycle multiply-accumulate keep tight loops like PID calculations or UART bit-banging running without wait-state stutter. The 6 KB SRAM is the hard limit for stack, buffers, and DMA descriptors; a design that needs a large Ethernet or USB packet buffer will overflow here. The 8-channel 10-bit ADC samples at a rate suitable for reading potentiometers, thermistors, or current-sense resistors; it won't do audio or high-speed data acquisition.
It comes in a 64-LQFP package with a 10x10 mm body and 0.5 mm pitch. That's a standard QFP footprint — no hidden thermal pad, no BGA rework challenges. A basic two-layer board with a ground plane under the MCU handles the 1.08 V to 1.32 V core supply rail without a dedicated power plane, as long as the local decoupling caps are within 5 mm of the VDD pins. The 33 I/O pins are 5 V tolerant on most ports, which simplifies level-shifting when interfacing to 5 V logic or older peripherals.
The LM3S1Z16-IQR50-C5 is listed as obsolete. TI no longer manufactures it, and no last-time-buy window is open.