Core architecture and memory map
The LM3S1R26-IQR80-C5T: On-chip memory comprises 256 KB of Flash and 48 KB of SRAM — enough for moderate-size control firmware with a real-time OS footprint.
Housed in a 64-LQFP package (10x10 mm body, 0.50 mm pitch), the part is surface-mount only. The 33 GPIOs bring out the peripheral set: I²C, SPI, SSI, UART/USART, IrDA, LIN, and Microwire. An internal oscillator eliminates the external crystal for the core clock, saving two pins on the layout.
On-chip peripherals and data conversion
Includes an 8-channel 10-bit ADC, brown-out detect, POR, DMA, PWM, and a watchdog timer. The DMA engine offloads the Cortex-M3 core during high-throughput serial transfers — useful when the UART or SPI is running near the bus clock.
Texas Instruments lists this part as Obsolete. No official successor is recorded.