50 MHz Cortex-M3 with on-chip flash and SRAM
The LM3S1958-IQC50-A2: The program memory is 256 KB of on-chip flash (256K x 8), paired with 64K x 8 of SRAM for data buffers and stack. Operating from a 2.25 V to 2.75 V supply rail, the part draws power from a regulated 2.5 V bus — not a standard 3.3 V rail — so the board-level regulator must be chosen for this narrower window.
Fifty-two GPIOs are available in the 100-LQFP package; the peripheral multiplexing includes I²C, SPI, SSI, UART/USART, and IrDA interfaces. The SSI port supports Microwire protocol, useful for legacy sensor interfaces. An internal oscillator eliminates the external crystal for basic timing, though the accuracy is limited to the internal RC tolerance. The ADC block provides 8 channels at 10-bit resolution — sufficient for reading potentiometers, current shunts, or temperature sensors without an external converter. On-chip peripherals include a PWM generator, watchdog timer, and brown-out detect with POR reset for supervised power-up.
NRND status and sourcing reality
For a BOM line already using this MCU, the NRND status means last-time-buy inventory is the supply path. Sourcing is handled per RFQ through independent distribution; quantities are lot-specific and confirmed at quote time. Any new design should evaluate the current Stellaris or Tiva C Series portfolio for a migration path, noting that the package and supply voltage may differ.