50MHz Cortex-M3 with 64KB Flash in a 100-LQFP
The LM3S1166-IQC50-A2: It packs 64 KB of flash and 16 KB of SRAM on a single-core die, with 43 general-purpose I/O lines brought out to a 100-pin LQFP (14×14 mm body).
On-chip peripherals and memory headroom
The 64 KB flash and 16 KB SRAM are modest by today's standards — enough for a single control loop, a Modbus RTU stack, or a sensor hub that offloads data via UART. The 4-channel 10-bit ADC (A/D 4x10b) samples analog inputs directly; no external ADC is needed for basic voltage or current sensing. Built-in peripherals include brown-out detect/reset, POR, PWM, and a watchdog timer. The PWM block can drive a small motor or LED dimmer without a dedicated PWM controller. Brown-out reset protects flash integrity during supply dips — useful in battery-powered or loosely regulated 2.5 V rails. The 100-LQFP package (0.5 mm pitch) requires a 4-layer PCB for reliable fan-out of the inner rows. The 14×14 mm footprint is standard for this pin count; thermal dissipation is adequate for the 50 MHz core at industrial temperatures without forced airflow.
Texas Instruments has marked the LM3S1166-IQC50-A2 as Obsolete. For a BOM line that requires this exact MCU, the supply posture is quoted-to-order.