Three-channel capacitive isolator with 5000 Vrms reinforced isolation
100 Mbps data rate with 16 ns propagation delay
The 1.3 ns typical rise and 1.4 ns fall times preserve signal integrity across the isolation barrier, while the 4.9 ns maximum pulse-width distortion keeps duty-cycle distortion low enough for most synchronous interfaces.
With a minimum common-mode transient immunity of 85 kV/µs, this isolator can reject the fast voltage transients present in motor-drive, inverter, and switched-mode power-supply applications. The 2/1 input-to-output channel split is a natural fit for isolating a three-wire SPI bus (SCLK, MOSI, MISO) where the chip-select is on the same side as the controller.
The base product number ISO7731 spans multiple channel configurations and directionality options, so the family is well-established with long-term supply visibility. The FDWR suffix denotes the 16-SOIC wide-body package on tape-and-reel, which is the standard ordering code for volume production.