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Texas Instruments ISO7241CDWRG4 — Digital Isolators

TI ISO7241CDWRG4 Quad-Channel Digital Isolator, 25 Mbps

MPNISO7241CDWRG4
End of Life

Texas Instruments ISO7241CDWRG4, General Purpose digital isolator, capacitive coupling, 4-channel unidirectional, 25 Mbps data rate, 2500 Vrms isolation, 3.15 V to 5.5 V supply, -40°C to 125°C, 16-SOIC.

$4.2400Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

ISO7241CDWRG4 specifications
ParameterValue
TypeGeneral Purpose
Channel typeUnidirectional
MountingSurface Mount
Supply voltage3.15V ~ 5.5V
Voltage - isolation2500Vrms
Isolated powerNo
Operating temperature-40°C~125°C
Pulse width distortion2.5ns
PackageTape & Reel (TR)
Data rate25Mbps
TechnologyCapacitive Coupling
Case16-SOIC (0.295\", 7.50mm Width)
Channels4
Inputs - side 1/Side 23/1
Rise (Fall time)2ns, 2ns
Propagation delay tpLH (tpHL)42ns, 42ns
Common mode transient immunity25kV/µs

Product details

Quad-channel capacitive isolator for industrial signal isolation

Its 25 Mbps data rate and 42 ns max propagation delay suit it for isolating SPI, UART, and general-purpose logic-level interfaces in motor drives, PLC I/O modules, and industrial fieldbus nodes.

25 Mbps with 42 ns propagation delay — timing budget for isolated links

At 25 Mbps the part handles a 40 ns bit period, and the 42 ns max propagation delay (tpLH / tpHL) means the total loop delay for a single direction is just over one bit time. That matters for SPI clock rates above 10 MHz where the master expects data back within a half-cycle — the designer needs to account for the isolator delay in the timing closure. The 2.5 ns max pulse-width distortion keeps the duty-cycle error small enough for UART framing at 115200 baud without bit-slip.

2500 Vrms isolation and 25 kV/µs CMTI — noise rejection in harsh environments

Rated for 2500 Vrms basic isolation per the device class, with a minimum common-mode transient immunity of 25 kV/µs. That CMTI figure is the key spec for motor-drive applications where the inverter switching generates fast common-mode voltage swings on the bus — if the isolator cannot reject those edges, data corrupts. The 2 ns typical rise/fall time keeps the output edges clean enough for the downstream logic without excessive ringing.

Channel configuration: three inputs on side 1, one on side 2

The channel direction map is 3/1 — three channels drive from side 1 to side 2, one channel drives from side 2 to side 1. That asymmetric layout fits the common industrial pattern where a microcontroller on side 1 sends multiple control signals (chip select, clock, data) across the barrier and receives a single feedback or data-ready signal back. The unidirectional channel type means each channel is fixed-direction, so the designer must match the signal flow to the pin assignment before layout.

Active lifecycle — no near-term obsolescence pressure

Frequently asked questions

Is ISO7241CDWRG4 obsolete or nearing end-of-life?

It remains a current-production TI part suitable for new designs.