Each of the four receivers handles 400 Mbps, which translates to a 200 MHz clock-equivalent data rate for double-data-rate schemes or 400 MHz for single-edge clocking.
Package and footprint notes for the layout engineer
MSL is not specified in this listing, but TI typically rates TSSOP packages at MSL 1 or 2 — verify the reel label for bake requirements if the moisture barrier bag has been open. The supply decoupling should use a 0.1 µF ceramic per receiver pair placed close to the VCC pins.