What this LVDS receiver does on the board
It handles four independent channels with a per-channel data rate up to 400 Mbps, making it a fit for high-speed serial interfaces like display links, camera serial interfaces, or backplane clock distribution where the signal has already travelled a cable or a long trace.
The 400 Mbps data rate is the per-channel maximum; with four receivers you can aggregate up to 1.6 Gbps of total throughput into the FPGA or ASIC on the other side. At this speed the receiver's input threshold and common-mode range become the limiting factor on cable length — LVDS is specified for a 100 mV differential swing with a 1.2V common-mode, so the 400 Mbps rating tells you the part can recover that tiny signal with enough timing margin for a 10- to 20-metre twisted-pair run, depending on the cable quality. If your link runs at 250 Mbps or lower, you have healthy margin on setup and hold.
The 16-TSSOP package has a 0.65 mm lead pitch and a body width of 4.40 mm. That pitch is fine enough that a standard iron tip can bridge two pins if you get heavy-handed, but it is still hand-solderable with a fine chisel tip and flux. Under the hot-air station the thermal mass is low — the part heats up fast, so a 260°C profile with a 10-second dwell is enough; keep the nozzle at least 2 mm above the body to avoid lifting the adjacent passives.
The base part number DS90LV032 is a mature LVDS receiver family that has been in production for years, and TI continues to support it. The /NOPB suffix confirms RoHS3 compliance and lead-free finish, so it passes the usual environmental requirements for new builds.