Dual LVDS receiver at 400 Mbps — what the data rate tells you
It takes two differential LVDS signal pairs and converts them to single-ended CMOS logic levels. The 400 Mbps per channel data rate means it can handle a 200 MHz clock or a 400 Mbps serial data stream on each receiver — useful for high-speed backplane links, camera serial interfaces, or display interconnects where you need to recover a clean logic signal from a noisy twisted-pair or PCB trace.
For existing BOMs already using this part, the NRND flag means you should qualify a second source or a drop-in alternate before TI issues a last-time-buy notice.
Package and footprint — 8-WDFN with exposed pad
The DS90LV028ATLD comes in an 8-WDFN exposed pad package (supplier device package 8-WSON, 4x4 mm). The pad is also the ground connection, so the layout needs a solid via stitch under the part to the ground plane. Mounting is surface mount only.