400 Mbps — the bus margin decision
At 400 Mbps the receiver's input threshold and propagation delay budget matter more than the raw bit rate. For a 200 MHz pixel clock or a 100 MHz serial link, the 400 Mbps ceiling gives enough headroom that you don't need to worry about jitter accumulation across a short backplane trace. If the link runs at 400 Mbps line rate, check the setup-and-hold timing against the downstream FPGA or ASIC — the DS90LV012A's typical propagation delay is tight enough for most 3.3V logic families, but a long PCB trace adds flight time that eats into the margin.
The ROHS3 compliance (NOPB suffix) means it's lead-free and ready for RoHS-exempt or full RoHS builds.