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Texas Instruments DAC7565ICPW — Discrete Semiconductors

TI DAC7565ICPW 12-bit quad DAC, 10µs settling, 16-TSSOP

MPNDAC7565ICPW
End of Life

Texas Instruments DAC7565ICPW, 12-bit quad voltage-output DAC, String DAC architecture, 10µs settling, ±0.5 LSB INL, SPI/DSP interface, 2.7V–5.5V supply, -40°C to 105°C, 16-TSSOP tube.

$12.5Ref. price · indicative, final on quote
Packaging16-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

DAC7565ICPW specifications
ParameterValue
Output typeVoltage - Buffered
MountingSurface Mount
Reference typeExternal, Internal
Voltage - supply, analog2.7V ~ 5.5V
Voltage - supply, digital2.7V ~ 5.5V
Data interfaceSPI, DSP
Operating temperature-40°C ~ 105°C
PackageTube
ArchitectureString DAC
INL (DNL)±0.5, ±0.1
Settling time10µs
Number of bits12
Case16-TSSOP (0.173\", 4.40mm Width)
Differential outputNo
Number of d (A converters)4

Product details

12-bit quad DAC with 10 µs settling — the update rate ceiling

The DAC7565ICPW is a 12-bit quad voltage-output DAC from Texas Instruments, packing four independent converters into a 16-TSSOP package. Each channel settles to ±0.5 LSB within 10 µs, setting the per-channel update rate at 100 kSPS when the SPI bus runs at its rated clock — the limiting factor is the serial interface throughput, not the DAC core.

String DAC architecture — inherently monotonic

Built on a String DAC architecture, the DAC7565ICPW guarantees monotonicity across the full 12-bit range — no missing codes, even at the code transitions that trip up R-2R designs. The DNL is ±0.1 LSB typical, well below the 0.5 LSB threshold that can cause non-monotonic behaviour in a control loop. The output is buffered, so the DAC drives a 2 kΩ load directly without an external op-amp. The reference can be internal or external — the internal reference is trimmed to 2.5 V, but an external reference lets you set the full-scale range anywhere within the supply rails. The digital interface is SPI-compatible with a DSP-friendly frame-sync — the 16-bit word shifts in on the rising edge of SCLK, and the DAC outputs update on the rising edge of SYNC.

The 16-TSSOP package (4.4 mm body width) is the standard footprint for multi-channel DACs in this resolution class — the 0.65 mm pin pitch routes easily on a two-layer board. Lifecycle status is Active, ROHS3 compliant per.

Frequently asked questions

What is the settling time of DAC7565ICPW and why does it matter?

The settling time is 10 µs to ±0.5 LSB for a full-scale step. This sets the per-channel update rate at 100 kSPS when the SPI clock is fast enough — the DAC output settles before the next conversion starts. For a servo loop updating at 10 kHz, the 10 µs settling leaves 90 µs of margin per cycle for the ADC read and PID calculation.

Is DAC7565ICPW a drop-in replacement for DAC7750IPWP?

No. The DAC7750IPWP is a single-channel current-output DAC with 25 µs settling, while the DAC7565ICPW is a quad voltage-output DAC with 10 µs settling. The pinout differs (16-TSSOP vs 20-TSSOP), the output type is different (current vs voltage), and the supply voltage is different (10 V vs 2.7–5.5 V). A board respin is required.

What is the INL/DNL specification for DAC7565ICPW?

INL is ±0.5 LSB typical, DNL is ±0.1 LSB typical. The DNL is well within the ±0.5 LSB boundary for guaranteed monotonicity — the String DAC architecture ensures no missing codes across the full 12-bit transfer function.