10-bit dual DAC with 20 ns settling
The DAC5652AIPFB: Two 10-bit DACs in one package, each with a current-source architecture and unbuffered differential current output. The 20 ns typical settling time suits high-speed waveform generation — think arbitrary-function generators, direct-digital-synthesis front-ends, or fast-settling control loops where a slower DAC would limit the update rate. INL is ±0.25 LSB typical, DNL ±0.03 LSB typical — the DNL figure is tight enough that a monotonic transfer curve is expected across the full 10-bit range, which matters for closed-loop servo or calibration DAC applications where a non-monotonic step would cause a control reversal.
Parallel interface and single 3.3 V rail
Data interface is parallel — a direct bus connection to an MCU or FPGA without serial protocol overhead. Reference can be internal or external, giving the designer flexibility to match the full-scale range to the system reference.
48-TQFP footprint and industrial temperature grade
Housed in a 48-TQFP with a 7x7 mm body — standard fine-pitch QFP footprint. Surface-mount only; the tray packaging is typical for volume assembly.