Dual 12-bit current-sink DAC with LVDS — what the specs mean for your signal chain
The DAC3162IRGZT is a dual 12-bit digital-to-analog converter that outputs a current-sink signal, meaning the output current decreases as the digital code increases — a topology common in high-speed communications and arbitrary waveform generation where the load pulls the output to a positive rail. Its LVDS parallel data interface moves 12-bit words at high clock rates with low noise, making it a fit for baseband I/Q modulation in software-defined radio or direct-digital synthesis where the data bus must keep up with the sample rate without coupling digital switching noise into the analog output. The 10 ns typical settling time means the output reaches its final value within one LSB in that window — at a 100 MSPS update rate, the output has settled well before the next sample arrives, so the SFDR is limited by the DAC core linearity, not the slew rate.
Supply rails and reference — planning the power tree
Differential output means the DAC drives a complementary current pair — this rejects common-mode noise on the output lines and doubles the signal swing into a transformer-coupled load, which is standard practice when driving an IF or RF mixer.
Linearity and accuracy — 12 bits with ±0.5 LSB INL
The INL of ±0.5 LSB and DNL of ±0.4 LSB mean the DAC is monotonic and accurate to better than 1 LSB across the full output range — no missing codes, and the integral linearity error stays within half an LSB, which keeps the spurious-free dynamic range (SFDR) limited by the DAC core rather than the transfer function.