8-bit D flip-flop with master reset
The CY74FCT273TSOCT is an 8-bit D-type flip-flop from the 74FCT series, featuring a master reset input and non-inverted outputs on a positive edge trigger. Maximum propagation delay is 13ns at 5V with a 50pF load — this sets the data-to-output timing budget for synchronous bus interfaces and state machines running below 77 MHz.
Output drive and quiescent draw
Output current capability is 32mA source and 64mA sink per channel, sufficient to drive multiple LS/TTL loads or short PCB traces without external buffers. Quiescent current is 200 µA typical, a low static draw for a 5V octal register — the power budget stays under 1 mW per chip at idle, which matters in densely populated backplanes where hundreds of registers share a supply rail. Input capacitance is 5 pF per pin, keeping the bus load light on the driving device.
Package and assembly fit
The supplier device package is 20-SOIC. Surface-mount package suits mixed-signal PCBs where through-hole logic is being phased out of the BOM.
RoHS3 compliant (2011/65/EU + 2015/863), no exemptions needed — clears the compliance gate for EU-market equipment without a waiver review.