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Texas Instruments CDCU877RHAT — Clock & Timing ICs

TI CDCU877RHAT PLL Clock Driver, 400 MHz, DDR2, 40-VQFN

MPNCDCU877RHAT
End of Life

Texas Instruments CDCU877RHAT, PLL clock driver, DDR2 memory, 400 MHz max, 1:10 input:output, SSTL-18 I/O, 1.7V–1.9V supply, -40°C to 85°C, 40-VQFN (6x6) surface mount.

$9.59Ref. price · indicative, final on quote
Texas Instruments CDCU877RHAT datasheet (PDF)
Packaging40-VFQFN Exposed Pad
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CDCU877RHAT specifications
ParameterValue
MountingSurface Mount
Supply voltage1.7V ~ 1.9V
Frequency - max400MHz
Operating temperature-40°C ~ 85°C
PLLYes
InputSSTL-18
OutputSSTL-18
PackageTape & Reel (TR); Cut Tape (CT)
Main purposeMemory, DDR2
Case40-VFQFN Exposed Pad
Number of circuits1
Ratio - Input:Output1:10
Differential - Input:OutputYes/Yes

Product details

The Texas Instruments CDCU877RHAT is a 1.8V PLL clock driver designed specifically for DDR2 memory systems. It takes one differential SSTL-18 reference clock and fans it out to ten differential outputs, all running at up to 400 MHz.

The 1:10 ratio means one clean reference clock from the chipset or oscillator can feed ten DDR2 loads — typically multiple DIMM slots or a mix of memory and controller. At 400 MHz the PLL keeps output-to-output skew tight enough to hold the DDR2 setup-and-hold window across the whole bank. Both input and output are differential SSTL-18, so the part mates directly to DDR2 DRAM and chipset clock pins without level translation.

Industrial temperature and active lifecycle

The part is Active and RoHS3 compliant.

Frequently asked questions

What is the function of CDCU877RHAT?

It is a PLL clock driver for DDR2 memory. It takes one differential SSTL-18 input clock and distributes it to ten differential outputs at up to 400 MHz, providing the low-jitter reference clocks needed by DDR2 DRAM and memory controllers.

Is CDCU877RHAT compatible with DDR2 memory?

Yes, the part is specified for DDR2 memory clock distribution. Its SSTL-18 I/O levels and 400 MHz maximum frequency match the DDR2-800/1066 bus timing requirements.