350 MHz PLL clock generator for automotive SERDES and ADAS timing
It integrates a PLL and supports differential or single-ended inputs, producing output clocks in HCSL, LVCMOS, or LVDS formats at up to 350 MHz.
Output flexibility eliminates level translators
Three output standards — HCSL for PCIe reference clocks, LVDS for long-reach differential distribution, and LVCMOS for single-ended fan-out — let the same part drive multiple clock domains without external translation. The 350 MHz ceiling supports the SERDES reference clocks in ADAS camera links and infotainment video buses.
Package and mounting — QFN with wettable flank
Housed in a 24-VFQFN with exposed pad (4x4 mm body), the wettable flank option improves solder-joint inspection yield for automated optical inspection (AOI) in high-volume automotive assembly. Surface-mount with wettable flank is the preferred footprint for under-hood modules that undergo thermal cycling.
RoHS compliance is standard for the series.