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Texas Instruments CDCE62002RHBT — Clock & Timing ICs

TI CDCE62002RHBT Clock Generator, 1.175 GHz, 32-VQFN

MPNCDCE62002RHBT
Active

Texas Instruments CDCE62002RHBT, Clock Generator, PLL Yes, 1.175 GHz max, LVCMOS/LVDS/LVPECL I/O, 3V-3.6V, -40°C~85°C, 32-VQFN (5x5).

$8.6600Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CDCE62002RHBT specifications
ParameterValue
TypeClock Generator
MountingSurface Mount
Supply voltage3V ~ 3.6V
Frequency - max1.175GHz
Operating temperature-40°C~85°C
PLLYes
InputLVCMOS, LVDS, LVPECL, Crystal
OutputLVCMOS, LVDS, LVPECL
PackageTape & Reel (TR); Cut Tape (CT)
Case32-VFQFN Exposed Pad
Divider (Multiplier)Yes/No
Number of circuits1
Ratio - Input:Output2:2
Differential - Input:OutputYes/Yes

Product details

1.175 GHz PLL clock generator for SERDES and FPGA clock trees

The Texas Instruments CDCE62002RHBT is a single-circuit clock generator with an integrated PLL that synthesizes outputs up to 1.175 GHz. It accepts LVCMOS, LVDS, LVPECL, or crystal inputs and delivers LVCMOS, LVDS, or LVPECL outputs through a 2:2 input-to-output ratio, making it a fit for clock distribution in 10G Ethernet, wireless base stations, and FPGA-based data acquisition systems where jitter and frequency accuracy drive the link budget.

Multi-protocol I/O and supply margin

The differential input and output paths (both rated Yes) allow direct connection to high-speed SERDES reference clocks without external level translation.

Frequently asked questions

What is the maximum output frequency of CDCE62002RHBT?

The maximum output frequency is 1.175 GHz, which covers the reference clock requirements for 10G SERDES, JESD204B converters, and high-speed FPGA transceivers.

What input and output signal types does CDCE62002RHBT support?

Inputs accept LVCMOS, LVDS, LVPECL, or a crystal oscillator. Outputs can be configured as LVCMOS, LVDS, or LVPECL. Both input and output paths are differential-capable, simplifying connection to SERDES reference clock inputs.