60 MHz dual JK flip-flop in a 14-pin DIP
The CD74HCT73E is a dual JK flip-flop from the 74HCT series, each element storing one bit with complementary outputs and a reset function.
Speed, drive, and temperature envelope
With a 60 MHz maximum clock frequency and 38 ns propagation delay at 4.5 V into 50 pF, this flip-flop supports moderate-speed logic chains — the delay is the limiting factor for cascaded stages, not the toggle rate. Outputs source and sink 4 mA each, suitable for driving standard TTL loads or CMOS inputs on the same 5 V rail. Quiescent current sits at 4 µA, keeping the static power draw negligible in battery-backed or always-on sections.
Active lifecycle and compliance
The 10 pF input capacitance is typical for HCT logic, keeping the dynamic load on the driving stage predictable for timing closure in the clock tree.