14-SOIC AND gate: board-fit and parametric profile
The CD74HCT11MT is a triple 3-input AND gate from Texas Instruments' 74HCT series, packaged in a 14-SOIC body (0.154" wide, 3.90 mm) for surface-mount assembly. The 1.27 mm pitch SOIC footprint is a standard JEDEC outline, so the land pattern is shared across many 14-pin logic parts — no board spin needed for a drop-in replacement within the same package code. The 2 µA max quiescent current keeps the static power draw negligible — useful in mixed-signal boards where the logic rail shares a regulator with sensitive analog stages. If your system sees cold-soak at -55°C or junction temperatures near 125°C, this part holds its logic thresholds without derating.
Switching speed and output drive — what 28 ns and 4 mA mean
Maximum propagation delay is 28 ns at 4.5 V supply into a 50 pF load. That 28 ns window includes both the gate's internal delay and the output rise time into the capacitive load — in a 5 V system clocked at 20 MHz (50 ns period), the gate adds just over half a period of delay, so timing margin on a 3-input AND path is tight but workable for most combinatorial logic. For higher-speed buses, the 74LV11 peer runs at 7.9 ns. Output drive is symmetric at 4 mA source and 4 mA sink. That's enough to drive one or two standard 74HCT loads or a single LED through a 330 Ω resistor, but not multiple fan-outs into high-capacitance traces without buffering. The low-state (VOL) and high-state (VOH) levels stay within TTL thresholds across the full temperature range. Input logic levels are 0.8 V low and 2.0 V high — compatible with 5 V TTL and 5 V CMOS outputs. Because the thresholds are fixed, a 3.3 V output driving the input may not reliably reach the 2.0 V high threshold; use a level translator if the upstream device is 3.3 V.