Dual JK flip-flop in a 14-pin DIP
The CD74HCT107E: Each of the two elements stores one bit and toggles on the negative edge of the clock input, with a complementary output pair per flip-flop. The reset function overrides the clock and sets the outputs to a known state. Rated for a clock frequency up to 56 MHz, the part suits moderate-speed logic chains in through-hole designs where a 5 V rail is already present.
Temperature grade and output drive
This makes it viable for avionics bay, engine test cell, or outdoor telecom enclosures where the ambient swings well beyond commercial 0-70°C limits. Each output sinks or sources 4 mA (at Vcc = 4.5 V), which is typical for HCT family gates. The 4 mA drive directly interfaces with standard CMOS inputs and most TTL loads without a buffer stage. Propagation delay is 43 ns maximum at 4.5 V with a 50 pF load — this sets the timing budget for cascaded stages: two flip-flops in series add 86 ns of clock-to-output latency before the next logic decision. Quiescent current is 4 µA typical, so the part adds negligible static draw to the supply rail. Input capacitance is 10 pF per input, which matters for clock line loading when multiple flip-flops share a common clock trace.
Package and board-fit
Housed in a 14-pin PDIP (0.300-inch, 7.62 mm body width), the CD74HCT107E is a through-hole part that mounts directly into a standard 0.100-inch pitch DIP socket or solders into plated through-holes on a 2.54 mm grid. The 14-PDIP footprint is one of the most widely supported IC packages — it fits perfboard, stripboard, and most prototype PCBs without a custom footprint.