The CD74HCT03MT: This is a current-production part, not a last-time-buy or obsolete line. ROHS3 compliant per, meaning no RoHS exemption declarations are needed at the receiving end.
This is a quad 2-input NAND gate (four independent gates, each with two inputs) but with open-drain outputs instead of the usual totem-pole push-pull stage. The output can only sink current (4 mA rated low-level drive); it cannot source current. A pull-up resistor to VCC is required on each output to create a valid high logic level. The open-drain topology lets multiple gate outputs connect to the same pull-up resistor for wired-OR or shared-bus configurations without contention. This is the main reason to choose this part over a standard 74HCT00 quad NAND.
Temperature grade and propagation delay
This extends the usable ambient envelope for outdoor telecom, engine-bay, or thermal-cycling applications without needing a separate industrial-grade variant. Maximum propagation delay is 24 ns at 4.5 V supply with a 50 pF load. At 5 V the delay is typically shorter, but the 24 ns ceiling is the timing closure number for worst-case conditions across temperature and voltage. For bus cycles above ~20 MHz, this gate will be the timing bottleneck.
Supply rails and input thresholds
Input logic low threshold is 0.8 V max; input logic high is 2 V min. This means the gate accepts 3.3 V logic as a valid high (2 V is below 3.3 V) and 0 V as a valid low, making it usable in mixed-voltage systems without a level translator on the input side, provided the 3.3 V driver's Voh exceeds 2 V. Quiescent current is 2 µA max across temperature — negligible for battery-powered equipment where the gate sits idle between operations.
Housed in a 14-SOIC narrow-body package (3.90 mm body width, 0.154" pitch). The supplier device package is 14-SOIC, surface-mount only. The footprint matches standard SOIC-14 land patterns — no special pad geometry required for the open-drain outputs.