Dual decade counter in 16-SOIC — what the 35 MHz count rate buys you
Asynchronous reset — why it matters for state machines
The asynchronous reset on each counter element forces all outputs low without waiting for the next clock edge. In a production test jig or a fault-recovery sequence, this lets you clear the counter mid-cycle and restart from zero on the next negative edge. No clock-gating logic required — the reset pin overrides the clock.
No last-time-buy risk for ongoing production. ROHS3 compliant — no exemptions that would require a waiver for EU or California markets.
Available through independent distribution channels. For dual-sourcing resilience, the CD74HCT390E (through-hole, 27 MHz, 4.5 V supply) is a functional alternative if the board can accommodate a DIP footprint and the lower speed.