4-bit synchronous binary counter with up/down direction
The CD74HC191E is a 4-bit synchronous binary counter from the 74HC high-speed CMOS logic family, capable of counting up or down at rates up to 35 MHz. It clocks on the positive edge and includes an asynchronous reset that forces all outputs low independently of the clock state.
Count rate and reset behavior for timing applications
With a maximum count rate of 35 MHz, this counter suits frequency division, event counting, or state-machine sequencing where the input clock runs at moderate speeds. The synchronous timing means all four bits change on the same clock edge, avoiding ripple skew that accumulates in asynchronous counters. The asynchronous reset (active low on the /CLR pin) clears the counter without waiting for a clock edge — useful for power-up initialization or emergency reset in safety-critical logic paths. Because it bypasses the clock, the reset pulse width must meet the minimum specified in the datasheet to guarantee all flip-flops clear.
Supply range and temperature grade for board-level integration
Housed in a 16-pin DIP (0.300-inch row spacing), the through-hole package is breadboard-friendly and survives manual rework. The 7.62 mm body width fits standard 0.300-inch DIP sockets; the 2.54 mm pin pitch matches prototyping grids.
Production status and compliance for BOM planning
ROHS3 compliance (lead-free and exempt-free per EU 2015/863) means it ships without restricted substances — no additional exemption documentation is needed for most commercial and industrial assemblies. The 74HC family is widely second-sourced; pin-compatible equivalents from other manufacturers exist, though the exact AC/DC characteristics may differ slightly.