Priority encoding for digital bus arbitration
The CD74HC147M96 is a 74HC-series priority encoder that compresses nine active-low input lines into a four-bit binary-coded output, encoding the highest-priority active input. The 1 x 10:4 circuit means a single encoder stage handles up to nine request lines plus a strobe, mapping the active input with the highest priority to its corresponding 4-bit code — a common fit for interrupt controllers, keypad scanners, and data-bus arbitration in mixed-voltage 2V to 6V systems.
Supply voltage and temperature envelope
Output drive is specified at 5.2 mA source and 5.2 mA sink at the rated supply — this is the HC family's standard totem-pole output stage. For a 15 pF load at 5V, the output transition time stays under 20 ns, keeping the encoder's propagation delay within the bus-cycle budget of a typical 8-bit microcontroller interrupt path.
SOIC-16 package and surface-mount integration
Housed in a 16-SOIC package with a 0.154-inch body width and 3.90 mm body width, the CD74HC147M96 uses the standard JEDEC MS-012 footprint. The 1.27 mm pin pitch is layout-friendly on two-layer boards — no via-in-pad or microvia needed for fan-out. The supplier device package is 16-SOIC, matching the case code for automated pick-and-place and reflow profiling.
Active lifecycle and compliance
The part is RoHS3 compliant (EU 2015/863) and carries no halogen or antimony declarations that would block it from EU or California market shipments.