Dual JK flip-flop with negative-edge clocking
The Texas Instruments CD74HC107M is a dual 1-bit JK flip-flop in the 74HC CMOS logic family, clocked on the negative (falling) edge with complementary outputs and an asynchronous reset. This edge polarity distinguishes it from positive-edge-triggered JK types in the same family — if your existing BOM uses a 74HC112 or 74HC73, confirm the clock phase before substitution. Rated for a 60 MHz maximum clock frequency with a 29 ns maximum propagation delay (at 6 V supply, 50 pF load), this part supports moderate-speed counter, divider, and state-machine functions in industrial and instrumentation logic chains.
Supply range, temperature grade, and quiescent draw
The 4 µA typical quiescent current (Iq) keeps the static power budget negligible in battery-backed or always-on logic sections. The 10 pF input capacitance per channel is standard for 74HC logic and presents a light load to the driving gate.
SOIC-14 package and active lifecycle
Housed in a 14-lead SOIC (3.90 mm width, 0.154" body) with supplier device package 14-SOIC, the CD74HC107M mounts on standard surface-mount land patterns shared with other SOIC-14 logic parts. The tube packaging suits low-to-medium volume assembly; for reel quantities, confirm the packing option at order.