Dual JK flip-flop with 100 MHz clock ceiling
The CD74ACT112M is a dual JK flip-flop from TI's 74ACT family, clocked at 100 MHz with negative-edge triggering. Each of the two elements stores one bit and provides complementary Q and Q̅ outputs, plus independent Set (Preset) and Reset pins for asynchronous control.
Propagation delay and output drive at 5 V
Max propagation delay is 10.3 ns at 5 V into a 50 pF load — this sets the timing margin for the receiving latch in a synchronous bus. The output stage sources and sinks 24 mA, enough to drive a 50 Ω transmission line or a bank of LED indicators without a buffer.
Quiescent current and input capacitance
Quiescent current is 4 µA per device, negligible in a battery-backed or always-on subsystem. Input capacitance is 10 pF per pin — the clock-tree fan-out calculation should account for this when driving multiple flip-flops from a single 100 MHz source.