Quad 2-input NAND in 14-SOIC
The CD74ACT00M: A design that needs to hold logic states in a cold-soak chamber or near an exhaust manifold can use this part without a separate temperature-grade qualification.
13.2 ns propagation delay at 5 V, 50 pF
Maximum propagation delay is 13.2 ns with a 5 V supply driving a 50 pF load. That sets the practical data-path ceiling — for a combinatorial chain of four gates in series, the cumulative delay is about 53 ns before the output settles. Above that, the downstream register needs to account for hold-time margin or the path must be pipelined. Input logic thresholds are 0.8 V low and 2.0 V high, compatible with standard 5 V TTL and CMOS families. The 4 µA maximum quiescent current means the gate draws negligible standby power when the inputs are static — useful in battery-backed or power-sensitive sections of a mixed-signal board.