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Texas Instruments CD4518BPW — Interface & Transceivers

CD4518BPW Texas Instruments BCD Counter, 8 MHz, 16-TSSOP

MPNCD4518BPW
End of Life

Texas Instruments 4000B series dual BCD up-counter, CD4518BPW, 8 MHz count rate, 3 V to 18 V supply, 16-TSSOP package, surface mount.

$1.12Ref. price · indicative, final on quote
Packaging16-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
Series4000B
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CD4518BPW specifications
ParameterValue
Series4000B
Logic typeBCD Counter
Trigger typePositive, Negative
MountingSurface Mount
Voltage3 V ~ 18 V
Operating temperature-55°C ~ 125°C
ResetAsynchronous
TimingSynchronous
PackageTube
DirectionUp
Count rate8 MHz
Case16-TSSOP (0.173\", 4.40mm Width)
Number of elements2
Number of bits per element4

Product details

Dual BCD up-counter in the 4000B family

The CD4518BPW is a dual BCD up-counter from Texas Instruments' 4000B series, containing two independent 4-bit BCD counters in a single 16-TSSOP package. Each element counts up on the positive or negative clock edge, with an asynchronous reset that clears the counter regardless of the clock state.

Operates from 3 V to 18 V, covering the full 4000B CMOS supply window. The 8 MHz typical count rate sets the upper edge for cascaded counters in frequency division or event counting — above this rate the propagation delay through the internal flip-flops accumulates and the external clock must be derated for the full temperature span.

Package and board integration

The 0.173-inch (4.40 mm) width footprint matches industry-standard TSSOP-16 land patterns, and the supplier device package is also 16-TSSOP — no footprint ambiguity.

Frequently asked questions

What is the CD4518BPW's reset type and how does it behave?

The reset is asynchronous — asserting the reset input clears all four BCD counter bits immediately, independent of the clock state. This means the counter resets mid-cycle without waiting for the next clock edge, which is critical for power-on initialization or fault recovery in sequential logic.