105 MSPS dual-channel pipeline — what the sampling rate and architecture mean for your capture
The ADC12DC105CISQE/NOPB is a 12-bit pipelined ADC sampling at 105 MSPS on two channels simultaneously — each channel has its own track-and-hold and its own A/D converter, so the two input signals are captured at the same instant, not multiplexed. That simultaneous-sampling architecture is what sets this part apart from a single-channel ADC with an input mux: you get true I/Q sampling for quadrature receivers, or simultaneous voltage and current capture in power-monitoring applications, without the phase skew that a multiplexed front-end introduces. The pipelined topology trades latency for throughput — at 105 MSPS the pipeline depth is typically 5-7 clock cycles, which matters if you are closing a control loop on the converted data rather than just recording it.
Supply rails, reference, and interface — what to budget on the board
The reference can be either internal or external — using the internal reference saves a component but ties the full-scale range to the internal bandgap accuracy; an external reference lets you set the full-scale independently and improves gain drift if the reference is a precision part like the REF50xx series. Data comes out on a parallel bus — 12 bits wide plus the conversion clock and output-enable control. A parallel interface at 105 MSPS means the bus toggles at 105 MHz, so the PCB trace length matching and termination matter more than they would for a slower serial interface. The differential input stage expects a balanced signal — the common-mode voltage is set by the VCM output of the ADC, typically mid-supply. Driving it single-ended through a balun or an FDA like the LMH6554 is the usual approach.
Active lifecycle — sourcing posture
It is a standard catalog part available through authorized distribution.