Single-gate buffer for mixed-voltage bus isolation
The 74LVC1G126DBVRG4: The output enable pin lets you tristate the bus when the line is idle, which is useful in shared I²C or SPI lines where multiple drivers share a rail.
Output drive and 3-state control
With 32mA symmetric drive (both high and low), this buffer can handle moderate capacitive loads on short board traces. The 3-state output (controlled by the output enable pin) lets you disconnect the buffer from the bus when it is not actively driving, which is essential in shared-resource designs like a multi-master SPI or a data bus with several peripherals. The single-gate format means you use exactly one buffer per signal line — no wasted gates in a quad package.
The 74LVC1G126DBVRG4 comes in a SOT-23-5 package. The five-pin footprint fits into tight layouts near the processor or connector.
It is a standard-production 74LVC single-gate device, widely stocked across the distribution channel.