NRND status — plan your BOM transition
This means ST has flagged the part for eventual end-of-life; new production runs are not guaranteed, and the primary supply channel is the independent surplus and broker market. For a BOM line that requires long-term availability, the NRND status demands a transition plan — either a last-time buy or a qualification to a successor.
The STM8 core runs at 16 MHz, which delivers roughly 16 MIPS for register-to-register operations. That throughput is adequate for periodic sensor polling, LIN bus messaging, and PWM generation in automotive body or industrial control applications. It is not a candidate for high-speed signal processing or real-time audio — the 8-bit architecture and moderate clock limit instruction-heavy loops. Watch the bus turnaround when using the 12-bit ADC at its full sampling rate; the DMA peripheral helps offload data movement.
Memory map: 32 KB Flash, 2K RAM, 1K EEPROM
Program memory is 32 KB of Flash, with 2K x 8 of SRAM and a separate 1K x 8 EEPROM block.
Peripheral set and analog integration
The DAC is useful for a single analog output or as a reference for external circuitry. The 41 I/O in the 48-LQFP package leave most pins available after power and ground are allocated.
For long-term BOM stability, ask about the official successor or a pin-compatible drop-in from the STM8A family.