Active-low reset — common polarity, easy integration
The reset output is active low, meaning it pulls the reset line to ground when the supply is out of tolerance. Most MCUs, FPGAs, and DSPs expect an active-low reset input, so this part connects directly without inversion. The push-pull output stage sinks and sources current, so you don't need an external pull-up resistor — just route the output to the processor's reset pin.
140 ms reset timeout — enough for most power rails
The minimum reset timeout of 140 ms gives the power supply time to ramp up and settle before the processor begins executing code. This is a standard duration that covers most linear and switching regulators. If your supply has a very slow ramp (e.g., large bulk capacitance or a soft-start regulator), verify that 140 ms is sufficient — otherwise the processor might start before the rail is fully stable.