Four-rail supervisor in a six-pin SOT-23
It is designed for systems that need to sequence or protect multiple power domains — think FPGA core and I/O banks, multi-rail MCU boards, or telecom line cards where a single fault should hold the entire system in reset. The reset output is active low and open-drain, so it can be wire-ORed with other reset sources or pulled up to a different voltage than the monitored rails. The minimum reset timeout of 140 ms gives most processors and FPGAs enough time to complete a clean power-on reset sequence. Thresholds are 2.32 V and 3.08 V for two fixed channels, plus two adjustable channels set with an external resistor divider.
Active production, no LTB watch needed
ROHS3 compliant, so it passes current EU and UKCA material restrictions without an exemption review.