Dual-core M4/M7 — asymmetric multiprocessing on a single die
The STM32H745IIT6 is a 32-bit dual-core microcontroller from ST's STM32H7 series, combining an ARM Cortex-M7 core running at 480 MHz with a Cortex-M4 core at 240 MHz on the same die. This asymmetric architecture lets you offload real-time control loops or communications stacks to the M4 while the M7 handles number-crunching or DSP workloads — without a second chip. With 2 MB of Flash and 1 MB of RAM, there is room for a full RTOS on one core and bare-metal interrupt service on the other.
Memory map and firmware partitioning
The 2 MB Flash is organized as a single bank, but the dual-bank option in the STM32H7 family is not enabled on this variant — firmware updates over-the-air require a swap routine in the application, not a hardware bank switch. The 1 MB RAM (1M x 8) is split across multiple SRAM blocks: a 192 KB ITCM tightly coupled to the M7 instruction bus, a 64 KB DTCM for data, and the rest as AXI SRAM accessible by both cores. If you partition the firmware so the M4 runs from AXI SRAM and the M7 from TCM, you avoid bus contention on the main AXI matrix. The bootloader does not steal flash — the entire 2 MB is available to the application after reset.
Supply range and power sequencing
The Vcc/Vdd supply range is 1.62 V to 3.6 V, which covers both 1.8 V and 3.3 V logic rails. The core logic runs from an internal LDO or a dedicated SMPS (if the package variant includes the SMPS pin), but the 176-LQFP version relies on the LDO — keep the decoupling dense on the Vcap pins.
The EBI/EMI bus can gluelessly interface to external SRAM, NOR Flash, or an FPGA — useful if the 2 MB on-chip Flash is tight for a graphics frame buffer. The 28-channel 16-bit ADC and dual 12-bit DAC handle analog front-end tasks without an external converter. The internal oscillator is trimmed to 1% accuracy, enough for UART and CAN at typical baud rates, but the HSE crystal is recommended if Ethernet or USB need ±50 ppm clocking.
The base product number STM32H745 is in volume production, and the 176-LQFP package is a standard ST package option with multiple assembly sites. For a production program that needs dual-core performance and a stable supply, this part is a low-risk selection.
Pin compatibility within the STM32H74x/H75x family
The STM32H745IIT6 is pin-compatible with the STM32H743IIT6 in the same 176-LQFP footprint — the difference is the second Cortex-M4 core. If a design currently uses the single-core STM32H743, swapping to the H745 adds the M4 core without a board respin. The STM32H750 is a different density (128 KB Flash) and is not pin-compatible in all packages; check the STM32H7 reference manual for the exact pinout table before assuming a drop-in replacement.