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STMicroelectronics STM32F746BGT6 — Microcontrollers & Processors (MCU / MPU / DSP)

STM32F746BGT6 STM32 MCU, 216MHz, 1MB Flash, 208-LQFP

MPNSTM32F746BGT6
Active

STMicroelectronics STM32F7 series STM32F746BGT6, ARM Cortex-M7, 216MHz, 1MB Flash, 320K x 8 RAM, 168 I/O, 208-LQFP, -40 to 85°C, 1.7 to 3.6V.

$20.0500Ref. price · indicative, final on quote
Packaging208-LQFP
RoHSROHS3 Compliant
SeriesSTM32F7
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

STM32F746BGT6 specifications
ParameterValue
SeriesSTM32F7
MountingSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))1.7V ~ 3.6V
Operating temperature-40°C ~ 85°C (TA)
Speed216MHz
PackageTray
RAM size320K x 8
Core size32-Bit Single-Core
PeripheralsBrown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
ConnectivityCANbus, EBI/EMI, Ethernet, I²C, IrDA, LINbus, SAI, SD, SPDIF-Rx, SPI, UART/USART, USB OTG
Number of i (O)168
Core processorARM® Cortex®-M7
Case208-LQFP
Data convertersA/D 24x12b; D/A 2x12b
Program memory size1MB (1M x 8)

Product details

208-LQFP — footprint and rework

Housed in a 208-LQFP with a 28x28 mm body, the package is a large fine-pitch QFP — not a BGA, so visual inspection and hand-rework are possible with a decent hot-air station. MSL 3 out of the bag: bake before reflow if the moisture-barrier bag has been open longer than the floor-life window.

Frequently asked questions

What is the difference between STM32F746BGT6 and STM32F746ZG?

Both share the same Cortex-M7 core at 216 MHz and 1 MB Flash, but the package and pin count differ. The STM32F746BGT6 comes in a 208-LQFP, while the STM32F746ZG uses a 144-LQFP with fewer I/O. The 208-pin variant provides 168 I/O versus the 144-pin part's lower count, so the choice depends on how many peripherals and external bus lines the design needs to bring out.

What is STM32F746BGT6's listed speed?

The core runs at 216 MHz, which is the maximum clock for the ARM Cortex-M7 on this device. At that speed, the Flash needs at least one wait state configured before raising the core clock, or the first instruction fetch will hard-fault.