72 MHz Cortex-M3 with 1 MB Flash — the high-density STM32F103
It comes in a 144-pin LQFP package (20x20 mm body) with 112 general-purpose I/O lines. This is the high-density member of the STM32F103 line, suited for applications that need the largest on-chip Flash and RAM in the family along with the full complement of interfaces.
What the 72 MHz core and 1 MB Flash mean for the BOM
At 72 MHz the Cortex-M3 core delivers 1.25 DMIPS/MHz, enough for real-time control loops, protocol stacks, and moderate DSP tasks. The 1 MB Flash is the largest in the STM32F103 family — a firmware engineer can fit a full RTOS, a TCP/IP stack, USB host/device libraries, and a CANopen stack without external memory. The 96 KB SRAM provides headroom for multiple buffers and a modest heap. For designs that need more RAM, the FSMC interface on this 144-pin package can map external SRAM or NOR Flash. The 72 MHz PLL requires setting one flash wait state (per the reference manual) before raising the core clock above 24 MHz, or the first branch will hard-fault. The 112 I/O lines in the 144-LQFP package give the board designer flexibility to route multiple peripherals — CAN, USB, two SPI, three USART, and two I²C interfaces — without pin-mux conflicts.
The part is ROHS3 compliant. No stock or price figures are published here; submit an RFQ for a binding quote.