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STMicroelectronics STD16N60M2 — Discrete Semiconductors

STD16N60M2 N-Channel MOSFET, 600V, 12A, DPAK

MPNSTD16N60M2
Active

STMicroelectronics STD16N60M2, MDmesh™ M2 series, N-Channel MOSFET, 600V Vdss, 12A Id, 320mOhm Rds(on) at 10V, DPAK (TO-252) package, 110W power dissipation, 19nC gate charge.

$2.0200Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

STD16N60M2 specifications
ParameterValue
SeriesMDmesh™ M2
FET typeN-Channel
MountingSurface Mount
Drain to source voltage600 V
Drive voltage (Max rds on, min rds on)10V
Current - continuous drain (Id) @ 25°C12A (Tc)
Power dissipation110W (Tc)
Operating temperature150°C(TJ)
PackageTape & Reel (TR); Cut Tape (CT)
Vgs±25V
TechnologyMOSFET (Metal Oxide)
CaseTO-252-3, DPak (2 Leads + Tab), SC-63
Vgs(th) (Max) @ id4V @ 250µA
Rds on (Max) @ id, vgs320mOhm @ 6A, 10V
Gate charge (Qg) (Max) @ vgs19 nC @ 10 V
Input capacitance (Ciss) (Max) @ vds700 pF @ 100 V

Product details

600 V N-channel MOSFET in DPAK — MDmesh M2 series

The STD16N60M2 is a 600 V N-channel power MOSFET from STMicroelectronics' MDmesh M2 series, built with a strip-layout vertical DMOS process that delivers low on-resistance and reduced gate charge for high-frequency switching applications.

The 19 nC gate charge is notably low for its current rating, which reduces the crossover conduction loss during hard-switching transitions. This combination makes the part well suited for resonant and quasi-resonant topologies where both conduction and switching losses matter. Compared to older planar-generation 600 V parts in the same package, the MDmesh M2 structure delivers roughly half the gate charge for a similar Rds(on) figure, which translates directly into higher efficiency at frequencies above 70 kHz.

Package and thermal design — DPAK layout notes

The DPAK (TO-252) footprint is a standard surface-mount power package with the drain tab as the main heat path. The 110 W power dissipation rating assumes the tab is soldered to a sufficient copper area on the PCB — typically at least 1 in² of 2-oz copper on the top layer, with thermal vias to inner planes. The exposed tab carries drain potential, so the copper island must be electrically isolated or tied to the drain node.

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