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STMicroelectronics M95080-DRDW3TP/K — Memory (DRAM / SRAM / Flash / EEPROM)

STMicroelectronics M95080-DRDW3TP/K Automotive EEPROM

MPNM95080-DRDW3TP/K
Active

STMicroelectronics Automotive, AEC-Q100 series, M95080-DRDW3TP/K, 8Kbit SPI EEPROM, 20 MHz, 1.8V–5.5V, -40°C to 125°C, 8-TSSOP.

$0.8700Ref. price · indicative, final on quote
Packaging8-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
SeriesAutomotive, AEC-Q100
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

M95080-DRDW3TP/K specifications
ParameterValue
SeriesAutomotive, AEC-Q100
Memory typeNon-Volatile
MountingSurface Mount
Voltage1.8V ~ 5.5V
Frequency20 MHz
Memory interfaceSPI
Operating temperature-40°C ~ 125°C (TA)
PackageTape & Reel (TR) Cut Tape (CT)
TechnologyEEPROM
Memory size8Kbit
Memory formatEEPROM
Case8-TSSOP (0.173\", 4.40mm Width)
Memory organization1K x 8
Write cycle time - word, page4ms

Product details

AEC-Q100 qualified 8Kbit SPI EEPROM for automotive ECUs

The STMicroelectronics M95080-DRDW3TP/K is an 8Kbit SPI EEPROM from the Automotive, AEC-Q100 series, designed for non-volatile parameter storage in automotive electronic control units. Organised as 1K x 8 bits, this EEPROM stores configuration words, trim values, and diagnostic counters that must survive key-off cycles. The 4 ms write-cycle time per word or page allows the ECU to commit a full parameter block before the power-supply hold-up capacitor decays.

20 MHz SPI bus — margin for daisy-chained sensor clusters

At 20 MHz the SPI interface provides a 50 ns clock period, which leaves timing margin when routing through a connector to a remote sensor module. The 8-TSSOP package (4.40 mm wide) fits in space-constrained ECU layouts alongside the main microcontroller.

RoHS3 compliance satisfies EU Directive 2015/863 and avoids the need for exemption documentation.

Frequently asked questions

Is M95080-DRDW3TP/K RoHS compliant?

Yes, it is listed as ROHS3 Compliant, meeting the current EU RoHS directive without exemptions.

What is the memory organization of M95080-DRDW3TP/K?

The memory is organised as 1K x 8 bits, providing 8Kbit of non-volatile storage accessed via the SPI interface.

When sourcing M95080-DRDW3TP/K, what is the closest functional second-source?

The DRMF3TG/K variant matches the full 125°C range in a different package. Neither is a drop-in replacement; verify the temperature grade and package footprint against your design.