64Kbit I²C EEPROM with AEC-Q100 qualification
It is part of the Automotive, AEC-Q100 series, meaning it has been qualified to the AEC-Q100 stress test standard for automotive-grade ICs. This makes it suitable for use in vehicle body electronics, infotainment, ADAS modules, and other systems where reliability under temperature extremes and vibration is required.
1 MHz clock and 450 ns access — bus timing margin
The M24C64-DRDW8TP/K supports a 1 MHz I²C clock frequency with a 450 ns access time. For a 64Kbit device, 1 MHz is the standard fast-mode-plus speed; the 450 ns access time ensures the memory is ready for the next bus transaction within a single clock cycle at that rate. In a mixed-speed I²C bus, this part will not introduce wait states as long as the master respects the minimum SCL low and high times.
The non-volatile memory retains data across power cycles and through the full temperature range.
8-TSSOP package — footprint and assembly
Supplied in an 8-TSSOP package (0.173" body width, 4.40 mm), this is a standard surface-mount package for serial EEPROMs. The TSSOP-8 footprint is shared across many 64Kbit I²C EEPROMs from multiple manufacturers, which simplifies second-sourcing or board-level substitution.
The base product number is M24C64, and the suffix /K denotes the automotive-grade variant with AEC-Q100 qualification. ROHS3 compliance is confirmed.