AEC-Q100 32 Kbit EEPROM for the automotive bus
The STMicroelectronics M24C32-DRMN8TP/K is a 32 Kbit serial EEPROM on the I²C bus, organized as 4K x 8, and qualified to the AEC-Q100 automotive stress standard. This is the part you pick when the BOM calls for non-volatile parameter storage in an ECU, ADAS module, or any automotive domain controller where the standard 85°C commercial EEPROM would be marginal.
450 ns access and 1 MHz I²C — timing headroom on a loaded bus
The 1 MHz I²C interface clock and 450 ns access time together set the read-cycle timing. At 1 MHz the SCL period is 1 µs; the 450 ns access means the EEPROM can present data within half a clock cycle, leaving margin for bus capacitance and the master's setup time. If the bus has multiple slaves or long traces, that margin is what keeps the first byte from stretching the clock.
ROHS3 compliance is confirmed. This is a current-production part, not a last-time-buy scavenger hunt.