512 Kbit I²C EEPROM for automotive and industrial buses
The STMicroelectronics M24512-DRDW8TP/K is a 512 Kbit serial EEPROM on the I²C bus, organized as 64 K × 8 bits. It carries AEC-Q100 automotive qualification and operates over a -40°C to 105°C temperature range.
450 ns access time — bus timing headroom
The 450 ns access time is the time from the I²C address byte acknowledge to the first data byte on a random read. On a 1 MHz I²C bus (1 µs SCL period), this means the EEPROM releases data within half a clock cycle after the address ACK — no extra wait states needed for most MCU I²C peripherals.
The 105°C upper limit covers under-hood and engine-bay ambient temperatures where the PCB sees conducted heat from the engine block. The AEC-Q100 stress tests — extended temperature cycling, high-temperature operating life (HTOL), and electrostatic discharge (HBM/CDM) — are what the automotive OEM requires for PPAP submission. If your BOM targets a passenger-car ECU, this qualification is the gate.
Write cycle time and page write
The write cycle time is 4 ms for a word or a page write. On a 512 Kbit device, the page size is typically 64 bytes (the I²C EEPROM standard for this density). A 4 ms write window means the master must wait 4 ms after the STOP condition on a write before sending the next start — no polling of the ACK is needed if the master inserts a 4 ms delay.
No last-time-buy, no NRND flag, no official successor.