PSRR profile and noise-sensitive rail suitability
The LD56020J120R delivers 90 dB PSRR at 100 Hz, rolling off to 55 dB at 100 kHz. That 90 dB floor at line frequency means a 100 mV ripple on the input rail translates to roughly 3 µV at the output — clean enough to power an analog front-end or a VCO supply without an additional post-filter. Output is fixed at 1.2 V, positive polarity, with a single regulator delivering up to 200 mA. Maximum dropout is 0.19 V at full load, so the input rail needs at least 1.39 V to maintain regulation across the full current range.
Quiescent draw and always-on domain fit
Quiescent current is 25 µA typical. For a battery-powered sensor node that spends most of its life in a low-power sleep state, that Iq sits below the self-discharge rate of a typical coin cell — the regulator does not dominate the standby budget. An enable pin lets the system processor gate the regulator output for sequenced power-up or to cut power to a peripheral during deep sleep, pulling the load current to zero when the rail is not needed.
Package, temperature grade, and board integration
Housed in a 4-XFBGA package with a 0.69 x 0.69 mm FlipChip footprint — one of the smallest LDO packages available. The 0.4 mm ball pitch demands a controlled solder-paste print and a fine-pitch stencil; the board house should confirm capability before layout. Surface-mount assembly with Tape & Reel or Cut Tape packaging options.
Protection and compliance coverage
Built-in over-temperature and short-circuit protection eliminate the need for an external supervisor or current-limit resistor on the output — the regulator handles fault recovery autonomously. Lifecycle status is active, with ROHS3 compliance — no restricted substance exemptions that would block EU or global shipments.