The SI8641BD-B-IS2 comes in a 16-SOIC wide-body (0.295-inch, 7.50 mm width) package. The 7.50 mm body width is the standard for reinforced isolation — the creepage distance across the package sidewall meets the 5000 Vrms isolation rating, so the board layout does not need additional slotting or potting for basic reinforced isolation. Surface-mount assembly with a standard SOIC-16 footprint; the wide-body variant requires a larger pad pattern than the narrow 3.9 mm SOIC, so confirm the PCB land pattern before tape-out.
What the isolation and speed ratings mean for your design
5000 Vrms isolation voltage — this is the reinforced isolation class per IEC 60747-5-5, meaning the part can withstand a 5 kV RMS potential between the two sides for 60 seconds. For a motor-drive or grid-tied inverter where the high-voltage side sits at 400 VDC bus, this provides the safety margin required for operator-accessible interfaces. 150 Mbps data rate with 13 ns typical propagation delay — the 150 Mbps ceiling is set by the 13 ns max propagation delay (tpLH/tpHL). At 150 Mbps, the bit period is 6.67 ns, so the 13 ns delay is roughly two bit periods; the part will pass data at that rate, but the output lags the input by two clock edges. For SPI clock lines at 50 MHz (20 ns period), the 13 ns delay adds roughly 65 % of a clock period — budget this into the timing closure. 50 kV/µs common-mode transient immunity — this is the slew rate of a voltage transient that the isolator can reject without corrupting the output. In a motor-drive application where the IGBT switching node swings 600 V in 100 ns (6 kV/µs), the 50 kV/µs rating gives 8× margin. The part will not glitch on the gate-drive edges.
Channel configuration and supply flexibility
Four unidirectional channels with a 3/1 input-side/side-2 split — three channels drive from side 1 to side 2, one channel drives from side 2 to side 1. This is the common SPI isolator map: three forward (SCLK, MOSI, CS) and one reverse (MISO). The unidirectional channel type means each channel has a dedicated input and output; no bidirectional data lines. The 4 ns typical rise/fall time and 4.5 ns max pulse-width distortion keep the signal integrity clean across the full supply range.