Active production — design-in ready
The SI8641BA-B-IU: The 16-QSOP body is lead-free and compatible with standard reflow profiles.
Parametric fit — what 150Mbps and 13ns mean on your bus
Rated 150Mbps data rate with 13ns max propagation delay (tpLH/tpHL) — this is the channel's throughput ceiling. For a 100Mbps SPI clock, the 13ns delay adds less than one clock period of skew across the isolation barrier; the 4.5ns pulse-width distortion means the duty cycle holds within 5% at 100Mbps, so downstream logic sees a clean clock edge. 35kV/µs common-mode transient immunity (CMTI) — this is the key spec for motor-drive or inverter applications where the ground plane jumps during PWM switching. A 600V IGBT bridge switching at 10kHz generates dV/dt in the 10-20kV/µs range; the SI8641BA-B-IU's 35kV/µs rating gives 2x margin against false toggling on the output. The 3/1 channel split (three inputs on side 1, one on side 2) is unidirectional — data flows one way per channel. This suits a three-channel SPI bus (SCLK, MOSI, CS) with a single return path (MISO) across the barrier, or three digital sensor inputs with one status feedback line.
Package and supply — board-fit checklist
The difference is within PCB layout tolerance for most designs; verify the land pattern against the Skyworks package drawing before committing a board spin. Supply range 2.5V to 5.5V on both sides — no separate VDDIO rail needed. The same 3.3V or 5V rail can power both the input and output stages, simplifying the power tree. No isolated power converter required (the part does not include an integrated DC-DC). The 2.5ns rise/fall time (typical) means the output slew rate is fast enough to drive a 15pF load at 150Mbps without excessive ringing, but the fast edge also couples more switching noise back to the supply — a 0.1µF bypass cap within 2mm of each supply pin is the standard mitigation.